Routine Ga FIB TEM sample preparation of a 14nm FinFET device

Mar/21/2017
Check out this new application example on ultra-thin TEM specimen from a cutting-edge semiconductor device
In this application note, ultra-thin lamella preparation from the SRAM array of a commercial processor based on 14 nm technology node is shown.

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Routine Ga FIB TEM sample preparation of a 14nm FinFET device
Failure analysis of microelectronic devices requires routine TEM sample preparation. The lamellae must be site-specific with thicknesses compatible with the technology node. Here we demonstrate lamella preparation from the SRAM array of a commercial processor based on 14 nm technology node. The transistors in such chip are 3D devices known as FinFETs.
pdf – 1 MB

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