Failure Analysis of Integrated Circuits

The semiconductor industry continues to shrink the size of electronic devices; the current state-of-art commercial technology nodes for integrated circuits are 14 and 22 nm, however, yet to come are 10 and 7 nm technology nodes which are still in the developmental stage.
Such integrated circuits are multilayer structures whose key elements are multi-gate transistors, where a source-drain channel („fin“) is surrounded by a 3D gate.
  • A failure analysis process of such integrated circuits typically involves delayering and electrical nanoprobing. After the defective area is found a lamella containing the failure of interest can be prepared for TEM inspection.
  • So far, delayering has been performed mainly by means of mechanical polishing. However, for future devices mechanical polishing cannot be used due to micro and nano mechanical deformation and chemical interactions with polishing suspension.
  • TEM lamella preparation is done on FIB-SEM systems. These lamellae must be artefact-free with the thickness proportional to the technology node.

Failure analysis of integrated circuits typically includes:

  • Delayering and electrical probing in technology nodes of last generation
  • Preparation of TEM lamella from integrated circuits
  • FIB-SEM tomography for 3D structural analysis (3D BSE reconstructions) 
  • Electrical fault isolation (EBIC, EBAC)
  • Low voltage SEM inspection
Failure Analysis of Integrated Circuits
14 nm technology node Intel processor. A top view of the transistor contact layer after delayering by GIS-assisted Xe Plasma FIB etching, image obtained at an electron accelerating voltage of 500 V with the In-Beam detector

Related Application Notes

FIB Tomography of an Integrated Circuit
FIB tomography has become an important tool for studying materials at the micro and nano scale. Unlike a single cross-section, FIB tomography gives better understanding of the volume distribution, 3D structure and the relationship between three dimensional objects. TESCAN FIB-SEMs can be equipped with 3D Tomography - an optional software module for automated data acquisition and reconstruction.
pdf – 1.4 MB
Ultra-Thin TEM Lamella Preparation with Backside Polishing
We have developed a new method for TEM lamella lift-out using a nanomanipulator with a rotational tip and special holder geometry. This method allows lamella attachment and polishing from the back. After attachment, the lamella is ready for final polishing and in-situ HADF R-STEM imaging without breaking vacuum.
pdf – 1.9 MB
Visualization of doped active regions in semiconductor devices
The possibility of consistent and efficient inspection throughout the entire manufacturing process of semiconductor devices is one of the key attributes for high yields and profitability. Feedback on control of each manufacturing step is absolutely necessary, especially during the mass production of wafers (tens of millions of devices per week). Checking layer thicknesses, step coverage, geometry of critical details, depth of trenches, etc. is carried out in order to find defects, their origin and implement appropriate corrective measures.
pdf – 1.1 MB
High resolution large format imaging for die inspection
Visual inspection is an integral part of the production line in all semiconductor foundries. Most of the inspection techniques currently in use are optical-based which will face a resolution limit due to the continual reduction in the size of dies. TESCAN’s Image Snapper is a perfect substitution allowing nondestructive imaging based on the stitching of high magnification images resulting in one high resolution panorama image.
pdf – 1004 kB

Documents for download

Artefact-free top-down TEM sample preparation of a 14 nm FinFET device
Artefact-free lamella preparation by FIB is crucial for successful TEM analysis. One of the difficulties one faces during the preparation of such specimens is the appearing of curtaining; surface artefacts that arise when polishing a sample which consists of different materials, each with different milling rates.
pdf – 1.2 MB
Routine Ga FIB TEM sample preparation of a 14nm FinFET device
Failure analysis of microelectronic devices requires routine TEM sample preparation. The lamellae must be site-specific with thicknesses compatible with the technology node. Here we demonstrate lamella preparation from the SRAM array of a commercial processor based on 14 nm technology node. The transistors in such chip are 3D devices known as FinFETs.
pdf – 1 MB