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Failure Analysis of Integrated Circuits

The semiconductor industry continues to shrink the size of electronic devices and sub-20 nm technology nodes are already available.

Semiconductors

Failure Analysis of Integrated Circuits

Such integrated circuits are multilayer structures whose key elements are multi-gate transistors, where a source-drain channel („fin“) is surrounded by a 3D gate.

14 nm technology node Intel processor. A top view of the transistor contact layer after delayering by GIS-assisted Xe Plasma FIB etching, image obtained at an electron accelerating voltage of 500 V with the In-Beam detector

14 nm technology node Intel processor. A top view of the transistor contact layer after delayering by GIS-assisted Xe Plasma FIB etching, image obtained at an electron accelerating voltage of 500 V with the In-Beam detector

  • A failure analysis process of such integrated circuits typically involves delayering and electrical nano probing. After the defective area is found a lamella containing the failure of interest can be prepared for TEM inspection.
  • So far, delayering has been performed mainly by means of mechanical polishing. However, for future devices, mechanical polishing cannot be used due to micro and nanomechanical deformation and chemical interactions with polishing suspension.
  • TEM lamella preparation is done on FIB-SEM systems. These lamellae must be artefact-free with the thickness proportional to the technology node.

 

Failure analysis of integrated circuits typically includes:
  • Delayering and electrical probing in technology nodes of the last generation
  • Preparation of TEM lamella from integrated circuits
  • FIB-SEM tomography for 3D structural analysis (3D BSE reconstructions)
  • Electrical fault isolation (EBIC, EBAC)
  • Low voltage SEM inspection
  • Download our app notes

    TEM specimen prepared from a 66 nm SDRAM sample using the TESCAN S9000X Xe plasma FIB SEM

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  • SEM inspection of ICs at low beam energies

    pdf 1 MB Download
  • Ultra-Thin TEM Lamella Preparation with Backside Polishing

    pdf 2 MB Download
  • Artefact-free top-down TEM sample preparation of a 14 nm FinFET device

    pdf 1 MB Download
  • Routine Ga FIB TEM sample preparation of a 14nm FinFET device

    pdf 1 MB Download
  • Large-area Cross-sectioning for Failure Analysis of Advanced Packaging Technologies

    pdf 2 MB Download
  • Visualization of doped active regions in semiconductor devices

    pdf 1 MB Download
  • High resolution large format imaging for die inspection

    pdf 1,004 KB Download
  • FIB Tomography of an Integrated Circuit

    pdf 1 MB Download
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