Such integrated circuits are multilayer structures whose key elements are multi-gate transistors, where a source-drain channel („fin“) is surrounded by a 3D gate.
- A failure analysis process of such integrated circuits typically involves delayering and electrical nano probing. After the defective area is found a lamella containing the failure of interest can be prepared for TEM inspection.
- So far, delayering has been performed mainly by means of mechanical polishing. However, for future devices, mechanical polishing cannot be used due to micro and nanomechanical deformation and chemical interactions with polishing suspension.
- TEM lamella preparation is done on FIB-SEM systems. These lamellae must be artefact-free with the thickness proportional to the technology node.
Failure analysis of integrated circuits typically includes:
- Delayering and electrical probing in technology nodes of the last generation
- Preparation of TEM lamella from integrated circuits
- FIB-SEM tomography for 3D structural analysis (3D BSE reconstructions)
- Electrical fault isolation (EBIC, EBAC)
- Low voltage SEM inspection