Similarly, TSVs allow the integration of heterogeneous die that uses different process nodes and different manufacturing technologies. TSVs significantly increase the bandwidth between the logic chip and the memory (especially with wide memory interfaces) which cannot be achieved with conventional bond wires. However, there are concerns about the reliability of TSVs; it has been proven that thermal cycling/annealing can induce mechanical failure in TSVs. The differences in thermal expansion coefficients between Cu and the Si wafer lead to considerable thermal stress that has an impact on the device performance. Cu extrusion induced by thermal stress can cause both TSVs and adjacent interconnect structures to fail.
TESCAN can provide the semiconductor and packaging industries with a diverse range of systems and detectors to implement analytical techniques to study stress levels and Cu extrusion in TSVs. Our range of high-performance SEMs allows for high and ultra high-resolution imaging of TSV extrusion and physical inspection on its cross-section. Dual-beam systems allow for pinpointing failure sites and subsequent local inspection and characterisation of these failure sites with a single instrument. TESCAN Xe plasma FIB-SEM systems offer the essential power and speed for performing high-throughput analysis in TSVs.
Large area cross-section of a 3D IC showing 5 Cu TSVs and Cu bump contact in silicon. The cross-section was prepared in less than one hour using Xe plasma FIB
- TSVs range from 50 to 100 μm in length and 15 to 30 μm in diameter and usually are arranged in arrays (which could be over 500 µm), therefore cross-sectioning these structures can be challenging with conventional Ga ion sources.
- Large cross-sectioning make it possible to find and examine voids, delamination, cracks, and other defects present in TSVs.
- EDX and EBSD mapping analyses can be implemented to study the Cu microstructure and different grain size distributions in TSVs.
- Xe plasma FIB induces less amorphous damage compared to Ga, which is an advantage for EBSD analysis.
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- BSE cross-sectional view of 2.5D stacked-die showing two Cu TSVs passing through silicon interposer in order to connect upper metal layers to additional backside metal layers
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- Cross-section of 2.5D stacked-die showing a solder ball and two TSVs
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- Magnified image of a Cu TSV showing the solder bump, passivation layer, mold compound and liner oxide layer
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- Upper part of a TSV imaged with the SE detector
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- Bottom part of a TSV imaged with the BSE detector for grain contrast
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- EBSD maps of a set of 4 × 50 μm copper TSVs polished by plasma FIB showing an overlay of a SE image with the IPF orientation maps. Image taken from T.Hrncir, et.al. ISTFA 2014, p. 136