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Artefact-free top-down TEM sample preparation of a 14 nm FinFET device

Check out this new application example!

Artefact-free top-down TEM sample preparation of a 14 nm FinFET device

Find out how to prepare curtaining-free high-quality lamellae from semiconductor devices.

In this application note a new method of top-down lamella preparation in a Ga FIB-SEM machine is shown. Curtaining artifacts are mitigated due to the alternation of the ion incidence angle by tilting the sample mounted on a Rocking stage.

21.03.2017
  • Artefact-free top-down TEM sample preparation of a 14 nm FinFET device

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